10xEngineers

Extend LLVM for RISC-V: Add Your Own Custom Builtin and Instruction

Are you ready to dive deep into the world of compiler development ? Our team has created an exciting new tutorial that demonstrates how to extend LLVM to support a custom RISC-V instruction and corresponding clang builtin. This hands-on guide takes you through the entire process, from adding a new builtin function in Clang to implementing a custom instruction in the RISC-V backend.

The Power of Custom Instructions

Custom instructions allow you to extend the capabilities of a processor architecture, optimizing for specific use cases or adding entirely new functionality. This tutorial showcases how to integrate such custom instructions into the LLVM toolchain and add clang builtin to target these custom instructions. 

What You'll Learn

Our GitHub tutorial walks you through creating a custom “factorial” instruction for RISC-V. You’ll learn how to:

  1. Add a new clang builtin  
  2. Define a corresponding LLVM intrinsic
  3. Map the builtin to the intrinsic
  4. Implement the custom instruction in the RISC-V backend
  5. Test your new instruction using LLVM tools

Tutorial Highlights

The tutorial covers several advanced aspects of LLVM development:

  • Working with TableGen to define new instructions
  • Understanding  how custom instructions are integrated in LLVM backend
  • Manipulating LLVM IR and SelectionDAG for instruction selection
  • Using LLVM’s  tools to visualize the instruction selection process
  • Writing and running tests to verify your custom instruction

Each step is explained in detail, with code snippets, command-line instructions, and helpful diagrams to guide you through the process.

Who Is This For?

This tutorial is perfect for:

  • Compiler engineers looking to extend LLVM for custom architectures
  • RISC-V enthusiasts interested in adding new instructions
  • Computer architecture students exploring the intersection of hardware and software
  • Developers working on specialized processors or accelerators

While some familiarity with LLVM and RISC-V is helpful, our step-by-step guide provides enough context for those new to these technologies to follow along.

Ready to Extend LLVM?

We invite you to check out the full tutorial on our GitHub repository. Whether you’re looking to  add support for a new hardware instruction, or simply learn more about how LLVM works under the hood, this guide will provide you with valuable insights and hands-on experience.

Link to GitHub Tutorial

Get ready to push the boundaries of what’s possible with LLVM and RISC-V. Happy hacking!


Stay tuned for more innovations from 10xEngineers – your partner in advancing RISC-V technology.

Table of Contents

Get Your Free Consultation Now! Discover how our expertise can elevate your project