Accelerate Time-to-Market for RISC-V, Image Processors & Compilers
Teaming up with fabless SoC firms, we offer RISC-V verification and design services, alongside Image Signal Processing expertise. Our team of highly skilled professionals helps you scale your design, verification, and compiler units by providing the necessary resources.
Vision, language, multi-modal
MLIR, LLVM, hand-tuned kernels
Algorithms, tuning, imaging IP
Formal, functional, uncore IP
Critical design bugs found by formal that simulation missed
End-to-end latency achieved on medical endoscope imaging
Architectural coverage, unprivileged and privileged
Contributing to OpenHW CVA6 and core-v-verif
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What we do
Three practices, each backed by IP and tooling we’ve already shipped. Most engagements start in one and pull in the others.
Design & Verification
Silicon-grade verification and RTL design for RISC-V cores and hard SoC blocks — testplan to signoff, on your schedule.
Where simulation stops, proof begins. We prove NoC deadlock and livelock freedom, AXI4 protocol compliance, cache coherence, and complex RISC-V datapath correctness — driving critical properties from planning to convergence and signoff.
Coverage tells you when you’re done. We build test plans, functional models, test generators and regression automation methods, carrying a block from the very first testbench to signoff.
Toolchain, LLVM and bring-up work for RISC-V targets — developed and regressed on Cloud V, our on-demand CI with Linux shell, CI/CD scripting and QEMU modes.
The blocks around the core, ready to integrate: IOPMP for I/O physical memory protection, and Debug & N-Trace for core visibility during bring-up and post-silicon.
Imaging & Vision
A full ISP engineering practice — algorithm development, image quality tuning and hardware implementation — run on our own imaging platform.
Pipeline design from your spec or from scratch — demosaic, denoise, HDR fusion, colour and tone, modelled before anything reaches RTL.
Sensor bring-up and tuning to your IQ targets: spectral-calibrated white balance, noise reduction and colour calibration, judged on objective metrics.
The signed-off pipeline into silicon: RTL design, FPGA prototyping, area and latency optimisation, and verification of the imaging datapath.
Our own ISP platform is what the three services above are delivered on — one lineage from Python model to C reference to RTL, FPGA and ASIC. It keeps algorithm, tuning and hardware consistent instead of three teams re-deriving the same pipeline.
The pipeline on GPU — software-defined, for throughput and fast iteration.
High dynamic range for scenes one exposure can’t hold.
Polyphase scaling for video and imaging pipelines.
Image quality analysis and tuning software.
AI Infrastructure Software Services
Custom silicon can’t deliver on its promise without software built to match it. We engineer the full AI software stack — from model optimization to compiler development to hand-tuned runtime kernels — so your workloads run at peak efficiency on any hardware, standard or custom. The result: silicon that performs the way it was designed to, from day one.
Vision, language and multi-modal model deployment built for production. We handle SDK development and end-to-end application pipelines so your models ship ready to run.
Model compression and inference speed-up techniques tuned to your target hardware, cutting latency and footprint without sacrificing accuracy.
Deep expertise across frontend frameworks, MLIR and LLVM — building the compiler layer that connects your models to silicon.
Hands-on work with llama.cpp, IREE, Triton and hand-written C/Asm kernels to squeeze maximum performance out of your runtime.
Ways to work with us
We offer a diverse range of engagement options, to accommodate different degrees of collaboration and responsibility, thereby delivering customized solutions aligned with your unique operational needs.
Resource Augmentation
Our employees become part of your team.
You manage. Our engineers report into your leads and follow your process.
Team Augmentation
Dedicated lead on our end to manage work, but both teams operate as a unified entity.
We co-manage. Our lead runs our side; the two teams work as one.
Turnkey Project
Ensure timely and accurate project delivery without requiring individual interaction among team members.
We deliver. One interface — lead to lead. No day-to-day management on your side.
Not sure which model fits? Tell us the block and the deadline — we’ll tell you which one we’d recommend.
AXI4 formal VIP, IOPMP, Debug & N-Trace, imaging IP, LumaIQ and the Baltoro compiler stack — available under licence, no engagement required.
We build in the open.
We deliver under NDA.
Client work stays confidential, so you can’t audit it. Our open-source work is the substitute: the same engineers, the same standard, in public. Read the commits before you read our proposal.
OpenHW Foundation — core contributor to CVA6 and CORE-V Wally since 2021
RISC-V Certification Steering Committee — our coverage work under consideration as a basis for open-source certification
Andes Technology — compiler partner for AI compilation on AX46MPV cores
Bit manipulation, Zce, Zicond and scalar cryptography extensions, plus infrastructure across core-v-verif and cvw-arch-verif.
Open testplans and SystemVerilog coverpoints for RV32 and RV64 through RVA22S64 — the work now before the certification committee.
Vector instruction implementation and test generation in Force Simulator.
A complete open image signal processor — Python model through C, RTL and FPGA to ASIC.
Coverage collection from a device under test over the RISC-V Verification Interface.
On-demand CI for RISC-V development: Linux shell, CI/CD scripting and QEMU modes.
IP and tooling you can license today
Built inside client engagements, then hardened into products. Every one has a spec, a datasheet and an engineer who can walk you through it.
I/O physical memory protection for RISC-V systems.
Debug and instruction trace for core bring-up and post-silicon.
Scaling IP for video and imaging pipelines.
Ready-to-use formal IP for 100% AMBA AXI4 compliance.
On-demand CI environment for RISC-V software.
Open ISP, Python model through to ASIC.
GPU-accelerated, software-defined ISP.
High dynamic range imaging pipeline.
Image quality analysis and tuning software.
Their deep technical knowledge, hard work, and long-standing commitment to the RISC-V open-source ecosystem have made this project possible. The 10xEngineers liaisons contributed the coverpoints for virtual memory — the most complex portion of the functional coverage.
10xEngineers have made outstanding contributions to the OpenHW community since joining in 2021, playing a key role in advancing the functionality, verification, and compliance of CVA6 and CV-Wally. We are counting on them for advancing industrial-quality, open-source RISC-V cores.
The 10xEngineers team provided exceptional compiler expertise throughout the project. Their LLVM-based tool significantly reduced Error Detection Latency and improved the error coverage of our post-silicon tests.
Tell us what you're building
An engineer reads every message. If there’s a fit, we’ll suggest a 30-minute technical call — no discovery deck.
San Diego, CA, USA