Job Overview:
We are seeking an experienced Hardware Verification Engineer to join our dynamic and innovative hardware verification team. The ideal candidate will have expertise in SystemVerilog (SV), testbench development, verification methodologies, Universal Verification Methodology (UVM) is a plus. Prior experience in the embedded field, FPGA and Verilog designing will also be considered.
Responsibilities
- Develop and implement verification plans and testbenches using SystemVerilog and UVM.
- Collaborate with the design and verification teams to ensure comprehensive coverage.
- Utilize advanced verification methodologies to identify and resolve design issues.
- Contribute to the continuous improvement of verification processes and methodologies.
- Participate in code reviews and provide feedback on verification-related aspects.
- Maintain thorough documentation of verification activities and results.
Qualifications:
- Proven experience as a Hardware Design Verification Engineer.
- Experience with FPGA design and verification.
- Knowledge of embedded systems and related technologies.
- Experience with scripting languages Python, Perl, Bash
- Familiarity with industry-standard verification tools and frameworks.
- Ability to work in a fast-paced and collaborative environment.
Preferred Skills:
- Expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM).
- Proficiency in testbench development and verification methodologies.
- Strong understanding of the verification life cycle.
- Excellent problem-solving skills and attention to detail.