Polyphase Video Scaler
Overview
10xEngineers Polyphase Video Scaler is a high performance, high quality, video scaler IP core capable of scaling up or down the input video stream by any factor. The IP supports scaling from an arbitrary input resolution to a wide range of output resolutions for video and graphics applications. It is provided as a highly optimized, synthesizable soft IP core for AMD® Xilinx® Ultrascale+™ FPGA devices. While optimized for Xilinx® FPGAs, the IP core features an FPGA agnostic design that can be easily ported to other FPGA devices.
Features
Processing and Resolution
- High quality polyphase algorithm
- High resolution support from 240×240 to 4k
- Processing up to 4k@60 fps
- Features dynamic resizing built-in anti-aliasing
Architecture
- 1, 2 and 4 pixel per clock output
- 6, 8, 10 or 12 taps in horizontal and vertical direction
- Supports 8, 10 or 12 bit width video input
- Works on AXI Stream Protocol with AXI-4 Lite Programming Interface
- 64 Unique Phases
Video Formats
- RGB, YCbCr 4:4:4, 4:2:2 and 4:2:0 video input
- Frame Rate & Aspect Ratio Conversion
Programmability
- Number of taps, bit width and scaler coefficients
- Also available as human readable Verilog source Code
- Different Coefficients Sets Available on Demand
Applications
- Video Broadcasting and Professional Broadcast Equipment
- Video Streaming Media Solutions and Media Players
- HDMI Convertors, HDMI Switches & Mixers, HDMI Splitters and Multiviewers
- Advertising Displays & Multiscreen Video Walls
- VR (Virtual Reality) Headsets
- Video Conferencing
- Digital TV & Home Theaters
- Automotive and Surveillance Cameras
- Medical Imaging
Interface
Resource Utilization
The table shows resource utilization data for several configurations of this IP core. The resource utilizations are taken using the Out-of-Context flow with Vivado Design Suite. Because surrounding circuitry will affect placement, no guarantee can be given that these figures will be repeatable in a larger design. At a higher pixel rate the scaler can be optimized for utilizing URAMs instead of BRAMs. This can be seen in the last rows of the table below.
| FPGA | Scaler Configuration | Resource Utilization | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Max Width | Max Height | Input Format | Output Format | Pixel Bit Width | Taps | Pixels Per Clock | LUT | FF | BRAMS | URAMS | DSP | ||
| 1 | zu5ev | 3840 | 2160 | 420 | 420 | 8 | 6 | 1 | 3528 | 2442 | 13 | 0 | 44 |
| 2 | zu5ev | 3840 | 2160 | 420 | 420 | 8 | 12 | 1 | 7552 | 4116 | 22 | 0 | 80 |
| 3 | zu5ev | 3840 | 2160 | 420 | 420 | 10 | 12 | 1 | 10052 | 5524 | 36 | 0 | 80 |
| 4 | zu5ev | 3840 | 2160 | 420 | 420 | 12 | 6 | 1 | 5290 | 3384 | 21.5 | 0 | 44 |
| 5 | zu5ev | 3840 | 2160 | 420 | 420 | 12 | 12 | 1 | 11348 | 6886 | 36.5 | 0 | 80 |
| 6 | zu5ev | 4096 | 2160 | 444 | 444 | 8 | 6 | 4 | 14141 | 9425 | 0 | 18 | 198 |
| 7 | zu5ev | 4096 | 2160 | 444 | 444 | 10 | 6 | 4 | 15182 | 10452 | 0 | 18 | 198 |
| 8 | zu5ev | 4096 | 2160 | 444 | 444 | 12 | 6 | 4 | 22206 | 13902 | 0 | 18 | 198 |
Support (Device Family):
Synthesizable, technology independent soft IP Core for FPGA, ASIC and SoC devices
License: End User License Agreement