Polyphase Video Scaler IP
10xEngineers Polyphase Video Scaler IP is a high-performance scaling IP core for precise video and image upscaling or downscaling. This FPGA video processing solution delivers sharp, high-quality visuals with efficient resource use, ideal for display controllers, imaging pipelines, and embedded systems.
Features
Flexible Scaling
High-resolution support from 240×240 to 4k; Processing up to 4k@30 fps; Scale by arbitrary factors horizontally and vertically (not limited to integer ratios)
Polyphase Filter Engine
Programmable Coefficients
Separable H/V Filter Architecture
Adjustable Number of Taps & Phases
Highly optimized, synthesizable Soft-IP Core
Video format Support
Streaming & Programming Interface
Bypass / Pass-through Mode
Latency & Throughput
Native / inherent anti aliasing
Why Chose Our Scaler IP?
10xEngineers Polyphase Video Scaler is a high performance, high quality, video scaler IP core capable of scaling up or down the input video stream by any factor. The IP supports scaling from an arbitrary input resolution to a wide range of output resolutions for video and graphics applications. It is provided as a highly optimized, synthesizable soft IP core for AMD® Xilinx® Ultrascale+™ FPGA devices. While optimized for Xilinx® FPGAs, the IP core features an FPGA agnostic design that can be easily ported to other FPGA devices.
Our polyphase scaling algorithm is engineered for applications that demand premium image quality and broadcast-level performance. Compared to basic methods like nearest-neighbor or bilinear interpolation, the polyphase approach uses advanced multi-tap interpolation filters designed to deliver superior visual fidelity across all resolutions.
This technology provides a sharper, more detailed output with minimal aliasing and edge blurring, making it ideal for high-end video processors, AI upscaling engines, and professional display systems. By using larger interpolation filters than the standard 2×2 bilinear filter, the algorithm achieves an improved frequency response, resulting in crisper visuals and smoother gradients during both upscaling and downscaling operations.
Applications
Empower broadcasting devices with our Polyphase Video Scaler IP, enabling real-time 4K scaling, low latency, and exceptional visual fidelity across formats.
Broadcast Imaging

Enhance video conferencing systems using our Polyphase Video Scaler IP, delivering crystal-clear 4K visuals, efficient bandwidth use, and seamless format conversion.
Video Conferencing

Elevate your media wall solutions with our Polyphase Video Scaler IP, offering ultra-smooth 4K scaling, precise image alignment, and seamless multi-display integration.
Media Walls

Empower your VR headsets with our Polyphase Video Scaler IP, delivering ultra-low latency, sharp 4K visuals, and industry-standard immersive performance.
VR Headset

Optimize your medical imaging workflows with our Polyphase Video Scaler IP, enabling high-fidelity 4K scaling, preserved diagnostic detail, low-latency visualization, and superior DICOM-compatible image interpolation.
Medical Imaging

Resource Utilization
The table shows resource utilization data for several configurations of this IP core. The resource utilizations are taken using the Out-of-Context flow with Vivado Design Suite. Because surrounding circuitry will affect placement, no guarantee can be given that these figures will be repeatable in a larger design. At a higher pixel rate the scaler can be optimized for utilizing URAMs instead of BRAMs. This can be seen in the last rows of the table below.
| FPGA | Scaler Configuration | Resource Utilization | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Max Width | Max Height | Input Format | Output Format | Pixel Bit Width | Taps | Pixels Per Clock | LUT | FF | BRAMS | URAMS | DSP | ||
| 1 | zu5ev | 3840 | 2160 | 420 | 420 | 8 | 6 | 1 | 3528 | 2442 | 13 | 0 | 44 |
| 2 | zu5ev | 3840 | 2160 | 420 | 420 | 8 | 12 | 1 | 7552 | 4116 | 22 | 0 | 80 |
| 3 | zu5ev | 3840 | 2160 | 420 | 420 | 10 | 12 | 1 | 10052 | 5524 | 36 | 0 | 80 |
| 4 | zu5ev | 3840 | 2160 | 420 | 420 | 12 | 6 | 1 | 5290 | 3384 | 21.5 | 0 | 44 |
| 5 | zu5ev | 3840 | 2160 | 420 | 420 | 12 | 12 | 1 | 11348 | 6886 | 36.5 | 0 | 80 |
| 6 | zu5ev | 4096 | 2160 | 444 | 444 | 8 | 6 | 4 | 14141 | 9425 | 0 | 18 | 198 |
| 7 | zu5ev | 4096 | 2160 | 444 | 444 | 10 | 6 | 4 | 15182 | 10452 | 0 | 18 | 198 |
| 8 | zu5ev | 4096 | 2160 | 444 | 444 | 12 | 6 | 4 | 22206 | 13902 | 0 | 18 | 198 |
Support (Device Family)
Synthesizable, technology independent soft IP Core for FPGA, ASIC and SoC devices
License: End User License Agreement