10xEngineers

Polyphase Video Scaler IP

10xEngineers Polyphase Video Scaler IP is a high-performance scaling IP core for precise video and image upscaling or downscaling. This FPGA video processing solution delivers sharp, high-quality visuals with efficient resource use, ideal for display controllers, imaging pipelines, and embedded systems.

Features

Flexible Scaling

High-resolution support from 240×240 to 4k; Processing up to 4k@30 fps; Scale by arbitrary factors horizontally and vertically (not limited to integer ratios)

Polyphase Filter Engine

Multi-tap, multi-phase FIR filtering to provide high-quality interpolation and anti-aliasing

Programmable Coefficients

Support for dynamically or statically loaded coefficient banks

Separable H/V Filter Architecture

Horizontal and vertical filtering stages in series (to save resources)

Adjustable Number of Taps & Phases

Optionally configure number of taps (4, 6, 8, 10, &12) and 64 unique phases

Highly optimized, synthesizable Soft-IP Core

Highly optimized, synthesizable Soft-IP Core for AMD® Xilinx® Ultrascale+™ FPGA devices

Video format Support

RGB (4:4:4), YCbCr/YC 4:2:2 or 4:2:0, 8/10/12 bit per component (depending on configuration)

Streaming & Programming Interface

AXI-4-Stream for input/output video; AXI-4 Lite Programming Interface

Bypass / Pass-through Mode

Option to bypass the scaler (1:1 pass) for cases where scaling is not needed

Latency & Throughput

Low pipeline latency, supports full real-time throughput for many video formats

Native / inherent anti aliasing

No separate anti aliasing filter required

Why Chose Our Scaler IP?

10xEngineers Polyphase Video Scaler is a high performance, high quality, video scaler IP core capable of scaling up or down the input video stream by any factor. The IP supports scaling from an arbitrary input resolution to a wide range of output resolutions for video and graphics applications. It is provided as a highly optimized, synthesizable soft IP core for AMD® Xilinx® Ultrascale+™ FPGA devices. While optimized for Xilinx® FPGAs, the IP core features an FPGA agnostic design that can be easily ported to other FPGA devices.

Our polyphase scaling algorithm is engineered for applications that demand premium image quality and broadcast-level performance. Compared to basic methods like nearest-neighbor or bilinear interpolation, the polyphase approach uses advanced multi-tap interpolation filters designed to deliver superior visual fidelity across all resolutions.

This technology provides a sharper, more detailed output with minimal aliasing and edge blurring, making it ideal for high-end video processors, AI upscaling engines, and professional display systems. By using larger interpolation filters than the standard 2×2 bilinear filter, the algorithm achieves an improved frequency response, resulting in crisper visuals and smoother gradients during both upscaling and downscaling operations.

Applications

Empower broadcasting devices with our Polyphase Video Scaler IP, enabling real-time 4K scaling, low latency, and exceptional visual fidelity across formats.

Broadcast Imaging

Enhance video conferencing systems using our Polyphase Video Scaler IP, delivering crystal-clear 4K visuals, efficient bandwidth use, and seamless format conversion.

Video Conferencing

Elevate your media wall solutions with our Polyphase Video Scaler IP, offering ultra-smooth 4K scaling, precise image alignment, and seamless multi-display integration.

Media Walls

Empower your VR headsets with our Polyphase Video Scaler IP, delivering ultra-low latency, sharp 4K visuals, and industry-standard immersive performance.

VR Headset

Optimize your medical imaging workflows with our Polyphase Video Scaler IP, enabling high-fidelity 4K scaling, preserved diagnostic detail, low-latency visualization, and superior DICOM-compatible image interpolation.

Medical Imaging

Interface

Resource Utilization

The table shows resource utilization data for several configurations of this IP core. The resource utilizations are taken using the Out-of-Context flow with Vivado Design Suite. Because surrounding circuitry will affect placement, no guarantee can be given that these figures will be repeatable in a larger design. At a higher pixel rate the scaler can be optimized for utilizing URAMs instead of BRAMs. This can be seen in the last rows of the table below.

FPGAScaler ConfigurationResource Utilization
Max WidthMax HeightInput FormatOutput FormatPixel Bit WidthTapsPixels Per ClockLUTFFBRAMSURAMSDSP
1zu5ev384021604204208613528244213044
2zu5ev3840216042042081217552411622080
3zu5ev384021604204201012110052552436080
4zu5ev3840216042042012615290338421.5044
5zu5ev384021604204201212111348688636.5080
6zu5ev40962160444444864141419425018198
7zu5ev4096216044444410641518210452018198
8zu5ev4096216044444412642220613902018198

Support (Device Family)

Synthesizable, technology independent soft IP Core for FPGA, ASIC and SoC devices
License: End User License Agreement

Optimize your system with our advanced scaler IP core

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