Functional Verification
Your Functional Verification Sign-Off Partner
We take functional verification off your plate and bring it to sign-off, using AI-assisted regression and triage flows to catch the corner cases in simulation that would otherwise surface in silicon.
Bug Rate
Found 100+ critical bugs on recent projects
Coverage
Achieved 100% functional and code coverage closure
Sign-Offs
5 tape-out sign-offs over 5 years
RISC-V
Strategic Member since 2022
Our Expertise
01
RISC-V CPU Core Verification
Functional verification of out-of-order, server-class RISC-V cores, from front-end to execution units.
02
Microarchitecture Unit Level Verification
Block-level verification of the Load-Store Unit, Instruction Fetch Unit, Branch Predictor, Decode Unit, macro-op cache and L2 cache against spec.
03
UVM Testbench & Stimulus Development
Reusable, parameterized UVM testbenches with directed and constrained-random stimulus, scaling to multi-core (4/8/16) configurations.
04
Debug, Bring-up & Triage
Root-cause debug of RTL and DV issues across core bring-up, debug module, JTAG and trigger, with fast triage from regression failure to fix.
05
Functional & Code Coverage Closure
Coverage driven to 99-100%, with UCDB hole analysis, directed stimulus, and auditable waivers.
06
RISC-V ISA & Extension Verification
Vector (RVV), Hypervisor, PMP/Smepmp, CBO, debug/trigger, BF16 and custom extensions verified to spec.
07
RISC-V Compliance
ISA compliance via the official ACT and RISCOF frameworks, integrated into your environment.
08
AMBA Protocol Verification (AXI, AHB, APB, CHI)
Interface verification with reusable VIP, including in-house VIP to cut license dependency.
09
ISS Co-Simulation & Reference Modeling
Co-simulation against Spike and custom ISS golden models, with reference checkers for end-to-end validation.
10
Regression & CI Automation
Python, Bash and Makefile-driven regression pipelines, triage dashboards, and coverage reporting.
11
SoC & Non-Core Subsystem Verification
Interconnect, bridges, interrupt controllers, and die-to-die / UCIe interface verification.
12
RAS & Fault-Injection Verification
Error-injection, ECC, and reliability and serviceability verification for safety-critical silicon.
Domains we embed our Cores
Data Center & Server-Class CPUs
Chiplet based architectures
AI & Vector Acceleration
Neural Accelerator & DSPs
Embedded & Edge class Cores
Network-based communications subsystem
Recent Projects
case study
Out-of-Order Server-Class RISC-V Core
Multi-generation verification of a US client’s out-of-order server-class core. Verified the Load-Store Unit, Instruction Fetch Unit, Branch Predictor, Decode Unit, macro-op cache and execution units with UVM testbenches, closing 99-100% coverage and catching 100+ critical bugs before silicon.
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L2 Cache & TLB with CHI Coherence
Verified L2 data cache and associated TLB on the same core. Validated cache-line state transitions and coherence messaging over CHI, modelled prefetcher behaviour, and reached 100% functional and code coverage.
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Die-to-Die & Non-Core SoC Subsystems
Verified non-core SoC subsystems including interconnect, bridges, interrupt controllers and a die-to-die (UCIe) interface controller. Drove coverage closure with parameterized UVM and surfaced 600+ RTL and DV issues.
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RISC-V Core MMU and IOMMU Verification
Verified address translation on two fronts. On the core MMU: SV32, SV39 and SV48 page-table formats, multi-level page-table walks, TLB behaviour and SFENCE/SINVAL flush across privilege modes. On the IOMMU: 1- and 2-stage translation (VS-stage and G-stage), nested guest VA to GPA to PA flows, IOTLB behaviour, permission checks and fault handling, all cross-checked against Spike as the golden model.
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In-House AMBA VIP & Vendor Migration
Built in-house UVM VIP for AXI, AHB and CHI and migrated the environment off vendor VIP to cut license dependency, with configurable knobs for backwards compatibility and reusable checkers, coverage and assertions.
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CoreSwap: Replacing ARM Cortex-A5 with RISC-V CVA6 in an ARM SoC
Swapped an ARM Cortex-A5 for the open-source RISC-V CVA6 core inside an existing ARM-based SoC, then verified the replacement integrated cleanly. Validated the CVA6 against the SoC’s bus fabric and peripherals (AXI, APB), confirmed boot and interrupt behaviour, and re-ran system-level checks to prove functional parity after the swap.
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RISC-V Compliance (ACT / RISCOF)
Integrated the official RISC-V Architectural Compliance (ACT) and RISCOF frameworks into the client environment, authored SoC-specific configurations, and validated ISA compliance end to end. Worked with the OpenHW Foundation to port the certification tests to OpenHW cores including CV32E20 and CVA6.
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Neural Accelerator, DSP and Other IP Verification
Verified a broad range of accelerators and IP blocks beyond the CPU core. These include a VLIW vector / neural accelerator (FP8, BF16 and FP32 vector operations against IEEE-754, 25+ bugs found), a MIPI I3C v1.1.1 compliant controller, interrupt controllers and interconnect (CHI, regbus, Tilelink), NoC routing, DSP and memory generator IP, and bridge, FIFO and serial-peripheral blocks, with reusable UVM environments and third-party IP integration.
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Let's talk
Tell us about your verification timeline and target tape-out.